1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including wiring layout and a semiconductor device including wiring layers.
2. Discussion of the Background
In general, semiconductor devices include wiring layers and insulating films disposed between the wiring layers. These days, as the semiconductor devices are manufactured in micro-fabrication dimension, there is market demand for flattening the insulating films between the wiring layers.
As for the method of flattening the insulating films between the wiring layers, for example, a spin-coating method and an etch-back method are used. Herein, films formed through the spin-coating and the etch-back processes are called spin-on glass (SOG) films. Because mechanical strength of the SOG film is relatively low and the SOG film tends to absorb moisture resulting in reliability failures, an additional insulating film is usually formed on the SOG film.
Compared with insulating films formed by plasma chemical vapor deposition (plasma CVD), a drawback of SOG films is that they have poor mechanical strength and cracks can be easily generated by heat stress applied to the SOG film during manufacturing or while the semiconductor device is in use. It is known that cracks generated during manufacturing seriously affect the reliability of the semiconductor device.
Turning now to FIGS. 5, 6A and 6B, failure of interlayer insulating films including a SOG film in a semiconductor device 1000 is described below. FIG. 5 is an electron micrograph of a cross section of the semiconductor device 1000. FIG. 6A is a schematic view of the cross section of the semiconductor device 1000 shown in FIG. 5. FIG. 6B is a plan view illustrating a layout of wiring layers 50 and 130 in the semiconductor device 1000 shown in FIGS. 5 and 6A.
With reference to FIG. 5, when the first wiring layer 50 and the second wiring layer 130 have large areas, stress is generated in directions indicated by white arrows shown in FIG. 6A during a subsequent heating process due to a difference in coefficient of thermal expansion between the material of the wiring layers and the material of the interlayer insulating films. Then, due to the heat stress, a crack 17 is generated in interlayer insulating films 70 and 90 located beneath the second wiring layer 130.
In order to prevent this failure, several approaches are proposed. As one example, JP-H09-199587-A proposes that slits are formed in a wiring layer that has a relatively large area (wide).
However, although the wiring layer is designed to have a large area such that great current can flow, a cross-sectional area of the wiring layer through which the current flows is decreased by the slits, and thus the amount of the current flowing through the wiring layer may be decreased as well.
As another example, JP-2003-109957-A proposes etching a lower wiring layer such that a ratio of a line width to an interval between the lines remains a specified ratio.
However, because specifying the ratio of line width to interval between the lines in the lower wiring layers can impose stricter limitations on the layout of the wiring layers than minimum processing dimensions, and therefore, a horizontal size of the semiconductor may become large, which is a problem.
In view of the foregoing, there is market demand for a semiconductor device and a layout of wiring layers in the semiconductor device to prevent cracks in the interlayer insulating films including the SOG film without forming slits in the wiring layer or specifying the ratio of the line width to the intervals between the lines in the lower wiring layer.